It is necessary to initialize an FPGA by virtue of resets or other ways, in order to ensure the FPGA's proper and reliable operation. Yet, this topic is often neglected and reduced to using code patterns in Verilog or VHDL, with the false belief that if there's a reset, and it's used the way everyone else does, everything is fine.
This series of three pages is an attempt to outline the main considerations on this topic.
The first page explains why the common use of asynchronous resets works partially at best. Those not using asynchronous resets at all can safely skip it.
The second page discusses synchronous resets vs. asynchronous resets, as well as other options for initializing the logic.
The third page takes a more practical approach, and suggests a reset controller for bringing up the FPGA correctly after powerup as well as in response to a request for a reset by the user (e.g. a reset button).
So once again, these are the three pages, as links with their titles: