This series of three pages discusses what happens when there is more than one clock in an FPGA design (which is often the case), and how logic that is synchronous with different clocks should interact. In some cases, when the clocks are related, there's not much special attention needed. However when the clocks are unrelated, the story becomes more complicated.
This way or another, it's important that the FPGA design tools apply timing constraints in a way that reflects the actual relations between the clocks, and even more important, how the logic treats these clocks.
All this is discussed in these three pages: