OK, what’s this?
This page is the example part of another post, which explains the meaning of set_input_delay and set_output_delay in SDC timing constraints.
TimeQuest (Quartus’ timing analyzer) performs a timing analysis in four corners (maximal and minimal temperature, combined with maximal and minimal voltage). For each path, TimeQuest picks the result of the corner that had the worst slack. In the examples below, the worst case of these four corners is shown. Accordingly, the numbers, that appear for delays of FPGA logic elements, are different from one timing report to another.
Another post of mine discusses the creation of timing reports as shown below.
In accordance with that other post, the timing constraints behind the examples below are:
create_clock -name theclk -period 20 [get_ports test_clk] set_output_delay -clock theclk -max 8 [get_ports test_out] set_output_delay -clock theclk -min -3 [get_ports test_out] set_input_delay -clock theclk -max 4 [get_ports test_in] set_input_delay -clock theclk -min 2 [get_ports test_in]
Analysis of set_input_delay -max (setup)
Delay Model:
Slow 1100mV 0C Model
+------------------------------------------------------------------------------------------------------+
; Summary of Paths ;
+--------+-----------+-----------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+-----------+--------------+-------------+--------------+------------+------------+
; 12.341 ; test_in ; test_samp ; theclk ; theclk ; 20.000 ; 3.940 ; 7.499 ;
+--------+-----------+-----------+--------------+-------------+--------------+------------+------------+
Path #1: Setup slack is 12.341
===============================================================================
+--------------------------------+
; Path Summary ;
+--------------------+-----------+
; Property ; Value ;
+--------------------+-----------+
; From Node ; test_in ;
; To Node ; test_samp ;
; Launch Clock ; theclk ;
; Latch Clock ; theclk ;
; Data Arrival Time ; 11.499 ;
; Data Required Time ; 23.840 ;
; Slack ; 12.341 ;
+--------------------+-----------+
+---------------------------------------------------------------------------------------+
; Statistics ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
; Setup Relationship ; 20.000 ; ; ; ; ; ;
; Clock Skew ; 3.940 ; ; ; ; ; ;
; Data Delay ; 7.499 ; ; ; ; ; ;
; Number of Logic Levels ; ; 1 ; ; ; ; ;
; Physical Delays ; ; ; ; ; ; ;
; Arrival Path ; ; ; ; ; ; ;
; Clock ; ; ; ; ; ; ;
; Clock Network (Lumped) ; ; 1 ; 0.000 ; ; 0.000 ; 0.000 ;
; Data ; ; ; ; ; ; ;
; IC ; ; 2 ; 2.447 ; 33 ; 0.000 ; 2.447 ;
; Cell ; ; 2 ; 5.052 ; 67 ; 0.652 ; 4.400 ;
; Required Path ; ; ; ; ; ; ;
; Clock ; ; ; ; ; ; ;
; Clock Network (Lumped) ; ; 1 ; 3.940 ; 100 ; 3.940 ; 3.940 ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
Note: Negative delays are omitted from totals when calculating percentages
+-----------------------------------------------------------------------------------+
; Data Arrival Path ;
+----------+---------+----+------+--------+-------------------+---------------------+
; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ;
+----------+---------+----+------+--------+-------------------+---------------------+
; 0.000 ; 0.000 ; ; ; ; ; launch edge time ;
; 0.000 ; 0.000 ; ; ; ; ; clock path ;
; 0.000 ; 0.000 ; R ; ; ; ; clock network delay ;
; 4.000 ; 4.000 ; F ; iExt ; 1 ; PIN_AP17 ; test_in ;
; 11.499 ; 7.499 ; ; ; ; ; data path ;
; 4.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X48_Y0_N58 ; test_in~input|i ;
; 8.400 ; 4.400 ; FF ; CELL ; 1 ; IOIBUF_X48_Y0_N58 ; test_in~input|o ;
; 10.847 ; 2.447 ; FF ; IC ; 1 ; FF_X48_Y2_N40 ; test_samp|asdata ;
; 11.499 ; 0.652 ; FF ; CELL ; 1 ; FF_X48_Y2_N40 ; test_samp ;
+----------+---------+----+------+--------+-------------------+---------------------+
+-------------------------------------------------------------------------------+
; Data Required Path ;
+----------+---------+----+------+--------+---------------+---------------------+
; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ;
+----------+---------+----+------+--------+---------------+---------------------+
; 20.000 ; 20.000 ; ; ; ; ; latch edge time ;
; 23.940 ; 3.940 ; ; ; ; ; clock path ;
; 23.940 ; 3.940 ; R ; ; ; ; clock network delay ;
; 23.840 ; -0.100 ; ; ; ; ; clock uncertainty ;
; 23.840 ; 0.000 ; ; uTsu ; 1 ; FF_X48_Y2_N40 ; test_samp ;
+----------+---------+----+------+--------+---------------+---------------------+
This analysis starts in "Data Arrival Path" with setting the input port (test_in) at 4 ns as specified in the max input delay constraint, and continues that data path. Together with the FPGA’s own data path delay (7.499 ns), the total data path delay stands at 11.499 ns.
The clock path is then calculated in "Data Required Path", starting from the following clock at 20 ns. The clock travels from the input pin to the flip-flop (with no compensation for the clock network delay, since no PLL is involved). This calculation also takes the estimated jitter into account (by virtue of "clock uncertainty"). All in all, the clock path ends at 23.840 ns, which is 12.341 ns after the data arrived to the flip-flop. This is the constraint’s slack.
This analysis shows that the number to put on a set_input_delay -max constraint is the maximal clock-to-output of the external device that drives the input pin ( + the trace delay of the board). This conclusion is made because the number is used as the starting time of the data path.
Analysis of set_input_delay -min (hold)
Delay Model:
Slow 1100mV 85C Model
+-----------------------------------------------------------------------------------------------------+
; Summary of Paths ;
+-------+-----------+-----------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------+-----------+--------------+-------------+--------------+------------+------------+
; 0.770 ; test_in ; test_samp ; theclk ; theclk ; 0.000 ; 4.287 ; 3.057 ;
+-------+-----------+-----------+--------------+-------------+--------------+------------+------------+
Path #1: Hold slack is 0.770
===============================================================================
+--------------------------------+
; Path Summary ;
+--------------------+-----------+
; Property ; Value ;
+--------------------+-----------+
; From Node ; test_in ;
; To Node ; test_samp ;
; Launch Clock ; theclk ;
; Latch Clock ; theclk ;
; Data Arrival Time ; 5.057 ;
; Data Required Time ; 4.287 ;
; Slack ; 0.770 ;
+--------------------+-----------+
+--------------------------------------------------------------------------------------+
; Statistics ;
+---------------------------+-------+-------+-------------+------------+-------+-------+
; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ;
+---------------------------+-------+-------+-------------+------------+-------+-------+
; Hold Relationship ; 0.000 ; ; ; ; ; ;
; Clock Skew ; 4.287 ; ; ; ; ; ;
; Data Delay ; 3.057 ; ; ; ; ; ;
; Number of Logic Levels ; ; 1 ; ; ; ; ;
; Physical Delays ; ; ; ; ; ; ;
; Arrival Path ; ; ; ; ; ; ;
; Clock ; ; ; ; ; ; ;
; Clock Network (Lumped) ; ; 1 ; 0.000 ; ; 0.000 ; 0.000 ;
; Data ; ; ; ; ; ; ;
; IC ; ; 2 ; 2.028 ; 66 ; 0.000 ; 2.028 ;
; Cell ; ; 2 ; 1.029 ; 34 ; 0.290 ; 0.739 ;
; Required Path ; ; ; ; ; ; ;
; Clock ; ; ; ; ; ; ;
; Clock Network (Lumped) ; ; 1 ; 4.287 ; 100 ; 4.287 ; 4.287 ;
+---------------------------+-------+-------+-------------+------------+-------+-------+
Note: Negative delays are omitted from totals when calculating percentages
+----------------------------------------------------------------------------------+
; Data Arrival Path ;
+---------+---------+----+------+--------+-------------------+---------------------+
; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ;
+---------+---------+----+------+--------+-------------------+---------------------+
; 0.000 ; 0.000 ; ; ; ; ; launch edge time ;
; 0.000 ; 0.000 ; ; ; ; ; clock path ;
; 0.000 ; 0.000 ; R ; ; ; ; clock network delay ;
; 2.000 ; 2.000 ; R ; iExt ; 1 ; PIN_AP17 ; test_in ;
; 5.057 ; 3.057 ; ; ; ; ; data path ;
; 2.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X48_Y0_N58 ; test_in~input|i ;
; 2.739 ; 0.739 ; RR ; CELL ; 1 ; IOIBUF_X48_Y0_N58 ; test_in~input|o ;
; 4.767 ; 2.028 ; RR ; IC ; 1 ; FF_X48_Y2_N40 ; test_samp|asdata ;
; 5.057 ; 0.290 ; RR ; CELL ; 1 ; FF_X48_Y2_N40 ; test_samp ;
+---------+---------+----+------+--------+-------------------+---------------------+
+------------------------------------------------------------------------------+
; Data Required Path ;
+---------+---------+----+------+--------+---------------+---------------------+
; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ;
+---------+---------+----+------+--------+---------------+---------------------+
; 0.000 ; 0.000 ; ; ; ; ; latch edge time ;
; 4.287 ; 4.287 ; ; ; ; ; clock path ;
; 4.287 ; 4.287 ; R ; ; ; ; clock network delay ;
; 4.287 ; 0.000 ; ; ; ; ; clock uncertainty ;
; 4.287 ; 0.000 ; ; uTh ; 1 ; FF_X48_Y2_N40 ; test_samp ;
+---------+---------+----+------+--------+---------------+---------------------+
This analysis starts in "Data Arrival Path" with setting the input port (test_in) at 2 ns, as specified in the min input delay constraint, and continues that data path. Together with the FPGA’s own data path delay (3.057 ns), the total data path delay stands at 5.057 ns.
The clock path is then calculated in "Data Required Path", starting from the same clock edge at 0 ns. After all, this is a calculation of hold timing, so the question is whether the data wasn't changed at the input of the flip-flop before it managed to sample it.
The clock travels from the input pin to the flip-flop (with no compensation for the clock network delay, since no PLL is involved). This calculation also takes the estimated jitter into account (by virtue of "clock uncertainty"), but note that its value is as zero. All in all, the clock path ends at 4.287 ns, which is 0.770 ns earlier than the change of the data. Hence this number is the slack.
This analysis shows that the number to put on a set_input_delay -min constraint is the minimal clock-to-output of the external device that drives the input pin. This conclusion is made because the number is used as the starting time of the data path.
Analysis of set_output_delay -max (setup)
Delay Model:
Slow 1100mV 85C Model
+--------------------------------------------------------------------------------------------------------+
; Summary of Paths ;
+-------+---------------+----------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+----------+--------------+-------------+--------------+------------+------------+
; 2.651 ; test_out~reg0 ; test_out ; theclk ; theclk ; 20.000 ; -5.320 ; 3.929 ;
+-------+---------------+----------+--------------+-------------+--------------+------------+------------+
Path #1: Setup slack is 2.651
===============================================================================
+------------------------------------+
; Path Summary ;
+--------------------+---------------+
; Property ; Value ;
+--------------------+---------------+
; From Node ; test_out~reg0 ;
; To Node ; test_out ;
; Launch Clock ; theclk ;
; Latch Clock ; theclk ;
; Data Arrival Time ; 9.249 ;
; Data Required Time ; 11.900 ;
; Slack ; 2.651 ;
+--------------------+---------------+
+---------------------------------------------------------------------------------------+
; Statistics ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
; Setup Relationship ; 20.000 ; ; ; ; ; ;
; Clock Skew ; -5.320 ; ; ; ; ; ;
; Data Delay ; 3.929 ; ; ; ; ; ;
; Number of Logic Levels ; ; 0 ; ; ; ; ;
; Physical Delays ; ; ; ; ; ; ;
; Arrival Path ; ; ; ; ; ; ;
; Clock ; ; ; ; ; ; ;
; Clock Network (Lumped) ; ; 1 ; 5.320 ; 100 ; 5.320 ; 5.320 ;
; Data ; ; ; ; ; ; ;
; IC ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ;
; Cell ; ; 3 ; 3.929 ; 100 ; 0.000 ; 2.150 ;
; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ;
; Required Path ; ; ; ; ; ; ;
; Clock ; ; ; ; ; ; ;
; Clock Network (Lumped) ; ; 1 ; 0.000 ; ; 0.000 ; 0.000 ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
Note: Negative delays are omitted from totals when calculating percentages
+---------------------------------------------------------------------------------------+
; Data Arrival Path ;
+---------+---------+----+------+--------+------------------------+---------------------+
; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ;
+---------+---------+----+------+--------+------------------------+---------------------+
; 0.000 ; 0.000 ; ; ; ; ; launch edge time ;
; 5.320 ; 5.320 ; ; ; ; ; clock path ;
; 5.320 ; 5.320 ; R ; ; ; ; clock network delay ;
; 9.249 ; 3.929 ; ; ; ; ; data path ;
; 5.320 ; 0.000 ; ; uTco ; 1 ; DDIOOUTCELL_X48_Y0_N50 ; test_out~reg0 ;
; 7.099 ; 1.779 ; FF ; CELL ; 1 ; DDIOOUTCELL_X48_Y0_N50 ; test_out~reg0|q ;
; 7.099 ; 0.000 ; FF ; IC ; 1 ; IOOBUF_X48_Y0_N42 ; test_out~output|i ;
; 9.249 ; 2.150 ; FF ; CELL ; 1 ; IOOBUF_X48_Y0_N42 ; test_out~output|o ;
; 9.249 ; 0.000 ; FF ; CELL ; 0 ; PIN_AN17 ; test_out ;
+---------+---------+----+------+--------+------------------------+---------------------+
+--------------------------------------------------------------------------+
; Data Required Path ;
+----------+---------+----+------+--------+----------+---------------------+
; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ;
+----------+---------+----+------+--------+----------+---------------------+
; 20.000 ; 20.000 ; ; ; ; ; latch edge time ;
; 20.000 ; 0.000 ; ; ; ; ; clock path ;
; 20.000 ; 0.000 ; R ; ; ; ; clock network delay ;
; 19.900 ; -0.100 ; ; ; ; ; clock uncertainty ;
; 11.900 ; -8.000 ; F ; oExt ; 0 ; PIN_AN17 ; test_out ;
+----------+---------+----+------+--------+----------+---------------------+
Since the purpose of this analysis is to measure the output delay, it starts off in "Data Arrival Path" with the clock edge (at 0 ns) and adds the clock network delay to the flip-flop. From there it goes along the data path until the output is reaches a stable logic state. The calculation for this yielded 9.249 ns.
This is compared with the time of the following clock at 20 ns, minus the output delay. Minus the estimated jitter (0.1 ns in the case above). The data was calculated to be stable at 9.249 ns. This is compared with the time when it has to be stable, 11.9 ns, so the slack is 2.651 ns.
This demonstrates why the number that is used with set_output_delay -max should be the setup time that is specified for the input of the external device. This timing constraint is verified by calculating the difference between the total delay to valid data at the output, and the following clock’s time position. This difference is the goal to achieve. That’s exactly the definition of setup time: How long the data must be stable before the next clock.
Analysis of set_output_delay -min (hold)
Delay Model:
Fast 1100mV 0C Model
+--------------------------------------------------------------------------------------------------------+
; Summary of Paths ;
+-------+---------------+----------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+----------+--------------+-------------+--------------+------------+------------+
; 1.275 ; test_out~reg0 ; test_out ; theclk ; theclk ; 0.000 ; -2.255 ; 2.020 ;
+-------+---------------+----------+--------------+-------------+--------------+------------+------------+
Path #1: Hold slack is 1.275
===============================================================================
+------------------------------------+
; Path Summary ;
+--------------------+---------------+
; Property ; Value ;
+--------------------+---------------+
; From Node ; test_out~reg0 ;
; To Node ; test_out ;
; Launch Clock ; theclk ;
; Latch Clock ; theclk ;
; Data Arrival Time ; 4.275 ;
; Data Required Time ; 3.000 ;
; Slack ; 1.275 ;
+--------------------+---------------+
+---------------------------------------------------------------------------------------+
; Statistics ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
; Hold Relationship ; 0.000 ; ; ; ; ; ;
; Clock Skew ; -2.255 ; ; ; ; ; ;
; Data Delay ; 2.020 ; ; ; ; ; ;
; Number of Logic Levels ; ; 0 ; ; ; ; ;
; Physical Delays ; ; ; ; ; ; ;
; Arrival Path ; ; ; ; ; ; ;
; Clock ; ; ; ; ; ; ;
; Clock Network (Lumped) ; ; 1 ; 2.255 ; 100 ; 2.255 ; 2.255 ;
; Data ; ; ; ; ; ; ;
; IC ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ;
; Cell ; ; 3 ; 2.020 ; 100 ; 0.000 ; 1.296 ;
; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ;
; Required Path ; ; ; ; ; ; ;
; Clock ; ; ; ; ; ; ;
; Clock Network (Lumped) ; ; 1 ; 0.000 ; ; 0.000 ; 0.000 ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
Note: Negative delays are omitted from totals when calculating percentages
+---------------------------------------------------------------------------------------+
; Data Arrival Path ;
+---------+---------+----+------+--------+------------------------+---------------------+
; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ;
+---------+---------+----+------+--------+------------------------+---------------------+
; 0.000 ; 0.000 ; ; ; ; ; launch edge time ;
; 2.255 ; 2.255 ; ; ; ; ; clock path ;
; 2.255 ; 2.255 ; R ; ; ; ; clock network delay ;
; 4.275 ; 2.020 ; ; ; ; ; data path ;
; 2.255 ; 0.000 ; ; uTco ; 1 ; DDIOOUTCELL_X48_Y0_N50 ; test_out~reg0 ;
; 2.979 ; 0.724 ; RR ; CELL ; 1 ; DDIOOUTCELL_X48_Y0_N50 ; test_out~reg0|q ;
; 2.979 ; 0.000 ; RR ; IC ; 1 ; IOOBUF_X48_Y0_N42 ; test_out~output|i ;
; 4.275 ; 1.296 ; RR ; CELL ; 1 ; IOOBUF_X48_Y0_N42 ; test_out~output|o ;
; 4.275 ; 0.000 ; RR ; CELL ; 0 ; PIN_AN17 ; test_out ;
+---------+---------+----+------+--------+------------------------+---------------------+
+-------------------------------------------------------------------------+
; Data Required Path ;
+---------+---------+----+------+--------+----------+---------------------+
; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ;
+---------+---------+----+------+--------+----------+---------------------+
; 0.000 ; 0.000 ; ; ; ; ; latch edge time ;
; 0.000 ; 0.000 ; ; ; ; ; clock path ;
; 0.000 ; 0.000 ; R ; ; ; ; clock network delay ;
; 0.000 ; 0.000 ; ; ; ; ; clock uncertainty ;
; 3.000 ; 3.000 ; R ; oExt ; 0 ; PIN_AN17 ; test_out ;
+---------+---------+----+------+--------+----------+---------------------+
This analysis is similar to the max output delay, only it’s calculated against the same clock edge (and not the following one).
As before, the data path continues the clock path until the output is stable. The calculation for this yielded 4.275 ns.
This is compared with the time of the same clock at 0 ns, minus the output delay. Recall that the min output delay in the timing constraint is negative (-3 ns), which is why it appears as a positive number in the calculation.
Conclusion: The data was stable until 4.275 ns, and needs to be stable until 3 ns. That’s fine, with 1.275 ns as the slack.
This demonstrates why the number that is used with set_output_delay -min is the hold time, that is specified for the input of the external device, with a reversed sign. This timing constraint is verified by requiring that the total delay is larger than this given number. In other words, the data must be stable for that long after the clock. This is the definition of hold time.